@jakiman: err, sorry - how are you able to make statements of 4 year stability of a device that's available since less than 2 years? I'm not inclined to do a per-sentence reply here but let me say your whole conclusion chain once more is an example of "based on false assumptions" - you CAN NOT state something is safe based on a limited-duration random field test where you don't have control about *any* of the critical parameters like usage patterns, hell not even about feedback for problems.
Your arguments are like "sure this car's engine will last >1000 miles at full speed, as we've seen no defects here at the 250 miles checkpoint yet" - does this sound honest or reassuring?
What you *might* say to those asking "is it safe?": If you are using the commonly used 800MHz+undervolt setup, and your usage pattern is that of an average user then your chances that your device will survive at least 12 months after enabling that OC are for sure better than 50%.

@freemangordon: I mostly agree with you, even partially with your chain of evidence about edge steepness. You're missing just one detail about SmartReflex: it's not only the automatic control of regulators in twl4030, SM is also a whole bunch of measures *on OMAP* chip, one of which is (AIUI) that there are individual micro "regulators" for voltage/current/working-point of each gate or even transistor. Those can't get switched on or off, they are always active. And again AIUI the twl4030 regulators and all the undervolting just determines the *input* voltage to those micro regulators. So if you really want to undervolt the logic gates, you'd need to lower the VDD input voltage to those regulators to a level where they cease to function, which can't be a sane thing in my book. All the SM that you can enable or disable in twl4030 is just meant to operate those micro regulators on a voltage drop as low as possible, to save energy (which btw only makes sense because the switching regulators in twl4030 are of better efficiency than those SM linear micro regulators).
Regarding temperature, while we're talking energy consumption, I agree that it for sure makes a lot of difference. Nevertheless the main factor is current density and the fact that it has a certain threshold above which EM goes through the roof while below it there's almost no EM at all. On OMAP3430 it seems this threshold is somewhere in the range 500..600MHz. I'm taking these values as well as my idea that they are independent from the SoC's "peripheral components" from the fact that the datasheet doesn't mention any of those as being relevant for the calculation for estimated lifespan at different clock speeds. Sure exceeding max die temperature will massively increase EM even on lower current densities, but the datasheet clearly says that up to the maximum allowed operating temperature and core voltage and whatnot the CPU still can live for 100.000h@500MHz and only for 23.000h@600MHz. I think if there'd been a way to safely extend that period (or increase clock speed while keeping the period) then TI for sure would've mentioned that, as they are interested in selling chips with the best possible specs.
I still fail to see any competence in N900 community that would allow to invalidate what TI came up with about maximum ratings of their chips, and speculating about what will happen if we deliberately go beyond those specs is just that: speculations. I'm feeling my speculations are based on sound facts and reasonable extrapolations, and they make me think a OMAP3430 will last no longer than 300h *running* at 1GHz clock speed, no matter what you do to it, as long as it works at all at that clock speed and not simply degrades to a random generator due to too low core voltage. After that timespan of CPU running at that clock speed I'd expect ~5..10 of 100 devices starting to expose random failures which make the device useless.

/j